Circuit designers have at their disposal, a variety of different methods of implementing their circuit designs. One method involves incorporating their designs in dedicated custom integrated circuits (ICs). The initial cost is relatively high and the turn-around time for producing a first set of these semiconductor chips is relatively long. Another method involves the implementation of application-specific integrated circuits (ASICs). Time to market for ASICs are faster, and it is easier to implement design changes. A third alternative, which enjoys growing popularity, is utilizing programmable logic devices (PLDs).
A PLD is a semiconductor chip that contains an array of gates having programmable interconnections. The gates are programmed according to the specification provided by the circuit designer. In PLDs, the desired logic functions are implemented by using standard product terms (p-terms). This involves first performing an AND function on the input variables and then forming the sum of the products, usually by performing an OR function. Typically, a standard number of p-terms are input to one or more programmable output structures, known as a macrocells. The p-terms are derived by using a piece of hardware, known as a programmer. A programmer is typically coupled by a serial port to a microcomputer, on which some form of programmer software is run. The simplest kind of software enables a designer to select which fuses to burn. The designer decides the desired logic function, at the gate level, then lists the corresponding fuses. Other more sophisticated programmers allow designers to specify Boolean expressions or truth tables. The software handles the minimization, simulation, and programming steps automatically. This yields custom combination and even sequential logic on a PLD chip.
Historically, when PLDs were first introduced, they tended to be simple and were rather limited in the functions that they could perform. Typically, input signals were transmitted through bond pads of the PLD chip to an electrostatic protection network. Next, the input signals were buffered to enable the PLD to handle both transistor-to-transistor logic (TTL) as well as complementary metal oxide semiconductor (CMOS) signals. Following the input buffers was a programmable interconnect matrix for routing the various input signals to the appropriate macrocells. This scheme worked fine for moderate PLD designs.
However, due to advances in semiconductor technology, PLDs have become more powerful and complex. The functions of entire blocks of circuitry can be performed by a single PLD. Today, modern PLDs are several times larger than their predecessors. As the total number of inputs to the PLD and the number of macrocells for processing all these inputs increase, the routing matrix must also grow correspondingly in size. This large routing matrix acts as a huge capacitive load. Whereas the input buffers of prior art PLDs only had to drive a relatively small routing matrix, additional drive capability is required in order to properly drive the tremendous load associated with present day routing matrices. Hence, several stages of input buffers are presently being implemented for providing the requisite drive.
However, the downside to this approach is that the additional drivers introduce significant delays in the signal path. Moreover, the additional buffering increases die size which translates into higher production costs. Furthermore, once the input signals have been buffered to provide for increased drive capability, it would be beneficial to pass these highly driven signals through the routing matrix to the logic circuits of the PLD. The problem is that, in order to do this, the switches within the routing network must be made large enough to handle the large amounts of current associated with these signals. The routing network is comprised of upwards of tens of thousands of such switches. Increasing the size of all these switches substantially increases the PLD's die size. A bigger die size means that less dies (i.e., chips) can be fabricated per wafer. Hence, the cost per chip goes up.
If smaller switches were used in the routing matrix, then additional buffers need be implemented after the routing matrix so as to build the signals back up again. These additional buffers consume valuable die area as well as introduce addition delays in the signal path.
Thus, there is a need in the prior art for a PLD design which provides high-speed routing of input signals with the requisite degree of current for properly driving the PLD's circuits. It would be preferable if the routing matrix of such a design were 100% connectable and routable. It would also be preferable if the design could be implemented with minimal impact to die size.